Nereo Markulić

A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter

Kuba Rączkowski, Nereo Markulić, Benjamin Hershberg et al. · IEEE Journal of Solid-State Circuits · 2015 · 120 citations

Integrated Phase Noise, Clock Recovery, Data Converter +8

A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS

Nereo Markulić, Kuba Rączkowski, Piet Wambacq et al. · 2014 · 84 citations

In-band Phase Noise, Engineering, Clock Recovery +8

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

Nereo Markulić, Kuba Rączkowski, Ewout Martens et al. · IEEE Journal of Solid-State Circuits · 2016 · 83 citations

Fractional Spur Improvement, Fractional-order System, Clock Recovery +10

A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS

Jorge Lagos, Nereo Markulić, Benjamin Hershberg et al. · IEEE Journal of Solid-State Circuits · 2022 · 51 citations

Engineering, Calibration, Data Converter +11

A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion

Benjamin Hershberg, Davide Dermit, Barend van Liempd et al. · IEEE Journal of Solid-State Circuits · 2021 · 46 citations