King Ho Tam

Challenges in gate level modeling for delay and SI at 65nm and below

Igor Keller, King Ho Tam, Vinod Kariat · 2008 · 31 citations

Engineering, Vlsi Design, Stochastic Analysis +16

Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization

Lei He, Andrew B. Kahng, King Ho Tam et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2005 · 27 citations

Engineering, Computer-aided Design, Integrated Circuits +18

Design and manufacturing process co-optimization in nano-technology

Meng-Kai Hsu, Nitesh Katta, Homer Yen-Hung Lin et al. · International Conference on Computer Aided Design · 2014 · 27 citations

Process Co-optimization, Engineering, Vlsi Design +18

Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random $L_{\rm eff}$ Variation

Lei He, Andrew B. Kahng, King Ho Tam et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2007 · 22 citations

Engineering, Vlsi Design, Process Variation +17

Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation

Lei He, Andrew B. Kahng, King Ho Tam et al. · 2005 · 19 citations

Random Leff Variation, Electrical Engineering, Systematic Cmp Variation +14