J.-F. Naviner

Signal probability for reliability evaluation of logic circuits

Denis Teixeira Franco, Maí Correia R. de Vasconcelos, Lírida Naviner et al. · Microelectronics Reliability · 2008 · 90 citations

Engineering, Computer Engineering, Electrical Engineering +16

Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs

David Camarero, K. Ben Kalaia, J.-F. Naviner et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2008 · 67 citations

Engineering, Electrical Engineering, Analog Electronics +16

Reliability analysis of logic circuits based on signal probability

Denis Teixeira Franco, Mai Correia Vasconcelos, Lírida Naviner et al. · 2008 · 38 citations

Engineering, Computer Engineering, Electrical Engineering +17

Selective hardening methodology for combinational logic

Samuel Pagliarini, Lírida Naviner, J.-F. Naviner · 2012 · 31 citations

Engineering, Computer Engineering, Electrical Engineering +16

FIFA: A fault-injection–fault-analysis-based tool for reliability assessment at RTL level

Lírida Naviner, J.-F. Naviner, Elaine Crespo Marques et al. · Microelectronics Reliability · 2011 · 30 citations

Computing, Computer Systems, Fault Tolerance +15