Andreas Dixius

A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schüffny, Richard George et al. · IEEE Transactions on Biomedical Circuits and Systems · 2022 · 45 citations · Full text

Nm Fdsoi Soc, Neural Probes, Medical Electronics +24

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital\n Neuromorphic Computing

Sebastian Höppner, Yexin Yan, Andreas Dixius et al. · arXiv (Cornell University) · 2021 · 40 citations · Full text

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing

Sebastian Höppner, Yexin Yan, Andreas Dixius et al. · arXiv (Cornell University) · 2021 · 34 citations · Full text

Engineering, Processing Element Architecture, Computer Architecture +16

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications

Sebastian Haas, Tobias Seifert, Benedikt Nöthen et al. · 2017 · 31 citations

Wireless Communications, Engineering, Vlsi Design +20

Dynamic Power Management for Neuromorphic Many-Core Systems

Sebastian Höppner, Bernhard Vogginger, Yexin Yan et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2019 · 21 citations · Full text

Neurochip, Power-aware Computing, Electrical Engineering +15