Peter Celinski

Low power, high speed, charge recycling CMOS thresholdlogic gate

Peter Celinski, José F. López, Said F. Al-Sarawi et al. · Electronics Letters · 2001 · 44 citations

Compact parallel ( <i>m</i> , <i>n</i> ) counters based on self-timed threshold logic

Peter Celinski, José F. López, Said F. Al-Sarawi et al. · Electronics Letters · 2002 · 17 citations

State of the art in CMOS threshold logic VLSI gate implementations and systems

Peter Celinski, Sorin Cotöfană, José F. López et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2003 · 15 citations

Hardware Security, Logic Synthesis, Electrical Engineering +14

Delay analysis of neuron-MOS and capacitive threshold-logic

Peter Celinski, Said F. Al-Sarawi, Derek Abbott · 2002 · 13 citations

Time Delay System, Electrical Engineering, Engineering +12

Low depth, low power carry lookahead adders using threshold logic

Peter Celinski, José F. López, Said F. Al-Sarawi et al. · Microelectronics Journal · 2002 · 12 citations