Jeongho Hwang

A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

Kwanseo Park, Woorham Bae, Jinhyung Lee et al. · IEEE Journal of Solid-State Circuits · 2018 · 46 citations

Oversampling Pfd, Engineering, Clock Recovery +13

A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

Kwanseo Park, Kwang‐Ho Lee, Sung‐Yong Cho et al. · IEEE Journal of Solid-State Circuits · 2020 · 45 citations

Continuous-rate Referenceless Clock, Prototype Cdr Circuit, Cdr Circuit +8

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS

Jeongho Hwang, Hong-Seok Choi, Hyungrok Do et al. · 2019 · 21 citations

Photonics, 3-Tap Asymmetric Ffe, Engineering +11

32.4 A 0.4-to-1.2V 0.0057mm² 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement

Jun-Eun Park, Jeongho Hwang, Jonghyun Oh et al. · 2020 · 20 citations

Low-power Electronics, Electrical Engineering, Digital Low-dropout Regulators +11

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push–Pull CML Driver in 65 nm CMOS

Jeongho Hwang, Gyu-Seob Jeong, Woorham Bae et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2017 · 17 citations

Low-power Electronics, Electrical Engineering, Engineering +12