Abhishek Acharya

Impact of Gate–Source Overlap on the Device/Circuit Analog Performance of Line TFETs

Abhishek Acharya, Abhishek B. Solanki, S. Glass et al. · IEEE Transactions on Electron Devices · 2019 · 31 citations

Device Modeling, Electrical Engineering, Line Tfets +13

Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective

Abhishek Acharya, Abhishek B. Solanki, Sudeb Dasgupta et al. · IEEE Transactions on Electron Devices · 2017 · 28 citations

Device Modeling, Semiconductor Technology, Electrical Engineering +13

Investigation of Self-Heating Effect in Tree-FETs by Interbridging Stacked Nanosheets: A Reliability Perspective

Shobhit Srivastava, M. Shashidhara, Abhishek Acharya · IEEE Transactions on Device and Materials Reliability · 2022 · 21 citations

Engineering, Energy Efficiency, Mechanical Engineering +20

Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight

Shobhit Srivastava, Sourabh Panwar, Abhishek Acharya · IEEE Transactions on Electron Devices · 2022 · 20 citations

Performance Evaluation of High-κ Dielectric Ferro-Spacer Engineered Si/SiGe Hetero-Junction Line TFETs: A TCAD Approach

Sourabh Panwar, Shobhit Srivastava, M. Shashidhara et al. · IEEE Transactions on Dielectrics and Electrical Insulation · 2023 · 16 citations