S. Dey

Strain-engineering in nanowire field-effect transistors at 3 nm technology node

Taraprasanna Dash, S. Dey, Sanghamitra Das et al. · Physica E Low-dimensional Systems and Nanostructures · 2020 · 25 citations

Semiconductor Technology, Nanowire Field-effect Transistors, Electrical Engineering +8

Pure germanium epitaxial growth on thin strained silicon-germanium graded layers on bulk silicon substrate for high-mobility channel metal-oxide-semiconductor field-effect transistors

S. Dey, Shalik Ram Joshi, Domingo I. García-Gutiérrez et al. · Journal of Electronic Materials · 2006 · 21 citations

Electrical Engineering, Bulk Silicon Substrate, Engineering +5

Vertically-Stacked Silicon Nanosheet Field Effect Transistors at 3nm Technology Nodes

Taraprasanna Dash, S. Dey, E. Mohapatra et al. · 2019 Devices for Integrated Circuit (DevIC) · 2019 · 20 citations

Vertically-stacked Sns-fets, Vlsi Design, Engineering +16

Performance comparison of strained-SiGe and bulk-Si channel FinFETs at 7 nm technology node

Taraprasanna Dash, S. Dey, Soumyadeep Das et al. · Journal of Micromechanics and Microengineering · 2019 · 15 citations

Engineering, Silicon On Insulator, Semiconductor Device +16

Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes

S. Dey, J. Jena, E. Mohapatra et al. · Physica Scripta · 2019 · 15 citations