Keewon Cho

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications

Seongju Lee, Kyuyoung Kim, Sanghoon Oh et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 113 citations

Engineering, Computer Architecture, Hardware Systems +20

Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares

Joo-Young Kim, Woosung Lee, Keewon Cho et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2016 · 28 citations

Engineering, Mem Testing, Computer Architecture +16

A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories

Hyungsu Sung, Keewon Cho, Kunsang Yoon et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014 · 26 citations

Non-volatile Memory, Engineering, Vlsi Design +17

Fail Memory Configuration Set for RA Estimation

Hayoung Lee, Keewon Cho, Sungho Kang et al. · 2020 · 18 citations

Ra Estimation, Engineering, Measurement +16

Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation

Hayoung Lee, Joo-Young Kim, Keewon Cho et al. · IEEE Transactions on Reliability · 2018 · 15 citations

Engineering, Built-in Redundancy Analysis, Mem Testing +18