C.T. Lin

Thermal stability of TiN metal gate prepared by atomic layer deposition or physical vapor deposition on HfO2 high-K dielectric

Lei Wu, H.Y. Yu, X. Li et al. · Applied Physics Letters · 2010 · 46 citations

Engineering, Tin Metal Gate, Semiconductor Device +19

A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm<sup>2</sup> SRAM cell

Kuan‐Lun Cheng, Chung-Cheng Wu, Y.P. Wang et al. · 2007 · 37 citations

Engineering, Vlsi Design, Integrated Circuits +16

Evaluating effects of a prenatal breastfeeding education programme on women with caesarean delivery in Taiwan

C.T. Lin, Su‐Chen Kuo, Kuan‐Chia Lin et al. · Journal of Clinical Nursing · 2008 · 37 citations

A 0.18 μm CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications

C.H. Diaz, K.L. Young, Johnny Hsu et al. · 2003 · 36 citations

Low-power Electronics, Electrical Engineering, μM Cmos +13

A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f/sub T/ RFMOS and versatile, high-Q passive components for cost/performance optimization

C.H. Chen, Chia-He Chang, C.P. Chao et al. · 2004 · 29 citations

Foundry Soc Technology, Passive Elements, Foundry 90 +16