Ralph Halbach

Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection

Junjun Li, Robert Gauthier, Souvick Mitra et al. · 2006 · 35 citations

Low-power Electronics, Electrical Engineering, Engineering +7

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

Dimitris Kontos, K. Domański, Robert Gauthier et al. · 2006 · 25 citations

Electrical Engineering, Engineering, Vlsi Design +9

Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

Junjun Li, David Álvarez, Kiran Chatty et al. · 2006 · 24 citations

Sem Analysis, Electrical Engineering, Polysilicon Gate +10

Study of factors limiting ESD diode performance in 90nm CMOS technologies and beyond

Kiran Chatty, Robert Gauthier, C. Putnam et al. · 2005 · 20 citations

Engineering, Vlsi Design, Esd Diode Performance +18

On The Interaction of ESD, NBTI and HCI in 65nm Technology

Rahul Mishra, Subhasish Mitra, Robert Gauthier et al. · 2007 · 15 citations

Materials Engineering, Electrical Engineering, Sblk Pfet +15