Iyad Ouaiss

An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications

Meenakshi Kaul, Ranga Vemuri, S. Govindarajan et al. · 1999 · 85 citations · Full text

An effective design system for dynamically reconfigurable architectures

S. Govindarajan, Iyad Ouaiss, Meenakshi Kaul et al. · 2002 · 25 citations

Lossy Compression, Engineering, Architectural Engineering +21

Register Binding for FPGAs with Embedded Memory

Hassan Al Atat, Iyad Ouaiss · 2004 · 19 citations

Hardware Security, Register Binding, Engineering +12

Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers

Iyad Ouaiss, Ranga Vemuri · Design, Automation, and Test in Europe · 2001 · 17 citations

Hardware Security, Hardware Architecture, Engineering +12

Toward an Improvement of Engineering Teaming Skills Through an In-House Professionalism Course

Mohammad Abbas, Wissam Fawaz, R. Ghajar et al. · IEEE Transactions on Education · 2020 · 11 citations

Group Assessment, Project Management, Education +16