Abstract Silicon spin qubits are promising candidates for scalable quantum computers, due to their coherence and compatibility with CMOS technology. Advanced industrial processes ensure wafer-scale uniformity and high device yield, but traditional transistor processes cannot be directly transferred to qubit structures. To leverage the micro-electronics industry expertise, we customize a 300 mm wafer fabrication line for silicon MOS qubit integration. With careful optimization of the gate stack, we report uniform quantum dot operation at the Si/SiO 2 interface at mK temperature. We measure a record-low average noise with a value of 0.61 $${\rm{\mu }}{\rm{eVH}}{{\rm{z}}}^{-0.5}$$ μ eVH z − 0.5 at 1 Hz and even below 0.1 $${\rm{\mu }}{\rm{eVH}}{{\rm{z}}}^{-0.5}$$ μ eVH z − 0.5 for some operating conditions. Statistical analysis of the charge noise measurements show that the noise source can be described by a two-level fluctuator model. This reproducible low noise level, in combination with uniform operation of our quantum dots, marks CMOS manufactured spin qubits as a mature platform towards scalable high-fidelity qubits.

#	Concept	H-Index	Publications	Citations
1	Engineering	1	1	44
2	Applied Physics	1	1	44
3	Computer Engineering	1	1	44
4	Electrical Engineering	1	1	44
5	Physics	1	1	44

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