Low charge noise quantum dots with industrial CMOS manufacturing

Abstract

Abstract Silicon spin qubits are promising candidates for scalable quantum computers, due to their coherence and compatibility with CMOS technology. Advanced industrial processes ensure wafer-scale uniformity and high device yield, but traditional transistor processes cannot be directly transferred to qubit structures. To leverage the micro-electronics industry expertise, we customize a 300 mm wafer fabrication line for silicon MOS qubit integration. With careful optimization of the gate stack, we report uniform quantum dot operation at the Si/SiO 2 interface at mK temperature. We measure a record-low average noise with a value of 0.61 $${\rm{\mu }}{\rm{eVH}}{{\rm{z}}}^{-0.5}$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:mi>μ</mml:mi> <mml:mi>eVH</mml:mi> <mml:msup> <mml:mrow> <mml:mi>z</mml:mi> </mml:mrow> <mml:mrow> <mml:mo>−</mml:mo> <mml:mn>0.5</mml:mn> </mml:mrow> </mml:msup> </mml:mrow> </mml:math> at 1 Hz and even below 0.1 $${\rm{\mu }}{\rm{eVH}}{{\rm{z}}}^{-0.5}$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:mi>μ</mml:mi> <mml:mi>eVH</mml:mi> <mml:msup> <mml:mrow> <mml:mi>z</mml:mi> </mml:mrow> <mml:mrow> <mml:mo>−</mml:mo> <mml:mn>0.5</mml:mn> </mml:mrow> </mml:msup> </mml:mrow> </mml:math> for some operating conditions. Statistical analysis of the charge noise measurements show that the noise source can be described by a two-level fluctuator model. This reproducible low noise level, in combination with uniform operation of our quantum dots, marks CMOS manufactured spin qubits as a mature platform towards scalable high-fidelity qubits.