Shih-Hsu Huang

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process

Che-Wei Tung, Shih-Hsu Huang · IEEE Access · 2020 · 41 citations · Full text

Mac Architecture, Engineering, Vlsi Design +16

Minimizing peak current via opposite-phase clock tree

Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu · 2005 · 40 citations

Low-power Electronics, Electrical Engineering, Power-aware Computing +13

Type-matching clock tree for zero skew clock gating

Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho et al. · 2008 · 39 citations

Hardware Security, Logic Synthesis, Engineering +12

Clock period minimization with minimum delay insertion

Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang et al. · Proceedings - ACM IEEE Design Automation Conference · 2007 · 27 citations

Engineering, Computer Architecture, Computational Complexity +16

Fast multi-domain clock skew scheduling for peak current reduction

Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh · 2006 · 26 citations

Mathematical Programming, Engineering, Power Optimization (Eda) +18