Yuan-Kai Ho

Type-matching clock tree for zero skew clock gating

Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho et al. · 2008 · 39 citations

Hardware Security, Logic Synthesis, Engineering +12

Multiple chip planning for chip-interposer codesign

Yuan-Kai Ho, Yao‐Wen Chang · 2013 · 33 citations

I/o Buffers, Engineering, Vlsi Design +18

Escape Routing for Staggered-Pin-Array PCBs

Yuan-Kai Ho, Hsu-Chieh Lee, Yao‐Wen Chang · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2013 · 21 citations

Physical Design (Electronics), Staggered Pin Array, Pcb Routing +12

Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs

Yuan-Kai Ho, Hsu-Chieh Lee, Webber Lee et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2014 · 14 citations

Engineering, Computer Architecture, Flip-chip Designs +16

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization

Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho et al. · 2010 · 14 citations

Engineering, Vlsi Design, Computer Architecture +17