Narender Hanchate

LECTOR: a technique for leakage reduction in CMOS circuits

Narender Hanchate, N. Ranganathan · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2004 · 228 citations

Low-power Electronics, Electrical Engineering, Engineering +10

Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory

Narender Hanchate, N. Ranganathan · IEEE Transactions on Computers · 2006 · 37 citations

Engineering, Vlsi Design, Game Theory +16

A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors

Narender Hanchate, N. Ranganathan · 2004 · 23 citations

Low-power Electronics, Electrical Engineering, New Technique +13

A linear time algorithm for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise

Narender Hanchate, N. Ranganathan · 2006 · 19 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization

Narender Hanchate, N. Ranganathan · 2006 · 10 citations

Engineering, Vlsi Design, Game Theory +19