T. Tanabe

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture

Satoru Tanoi, T. Tanabe, Kazuhiko Takahashi et al. · IEEE Journal of Solid-State Circuits · 1996 · 21 citations

Reference Frequency Supply, Engineering, Vlsi Design +12

A 32-bank 256-Mb DRAM with cache and TAG

Satoru Tanoi, Y. Tanaka, T. Tanabe et al. · IEEE Journal of Solid-State Circuits · 1994 · 15 citations

Hardware Security, Electrical Engineering, Negative Conductance +15

A 32-bank 256 Mb DRAM with cache and TAG

Satoru Tanoi, Y. Tanaka, T. Tanabe et al. · 2002 · 13 citations

Engineering, Memory Design, Emerging Memory Technology +18

On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM

Satoru Tanoi, Y. Tokunaga, T. Tanabe et al. · IEEE Journal of Solid-State Circuits · 1997 · 10 citations

Hardware Security, Electrical Engineering, Memory Architecture +14