Satoru Tanoi

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture

Satoru Tanoi, T. Tanabe, Kazuhiko Takahashi et al. · IEEE Journal of Solid-State Circuits · 1996 · 21 citations

Reference Frequency Supply, Engineering, Vlsi Design +12

A 213-233 GHz ×9 Frequency Multiplier Chain with 4.1 dBm Output Power in 40nm Bulk CMOS

Ruibing Dong, Shinsuke Hara, Issei Watanabe et al. · 2021 · 20 citations

Engineering, Radio Frequency, Dbm Output Power +8

A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS

Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura et al. · 2011 · 16 citations

Frequency Multiplier, Phase Correction Points, High-frequency Device +6

A 32-bank 256-Mb DRAM with cache and TAG

Satoru Tanoi, Y. Tanaka, T. Tanabe et al. · IEEE Journal of Solid-State Circuits · 1994 · 15 citations

Hardware Security, Electrical Engineering, Negative Conductance +15

An inductorless injection-locked PLL with 1/2- and 1/4-integral subharmonic locking in 90 nm CMOS

Sang yeop Lee, Sho Ikeda, Hiroyuki Ito et al. · 2012 · 13 citations

Pll Area, Electrical Engineering, 1/4-Integral Subharmonic Locking +12