T. Shinbo

A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer

N. Ohkubo, Makoto Suzuki, T. Shinbo et al. · IEEE Journal of Solid-State Circuits · 1995 · 182 citations

Engineering, Computer Engineering, Electrical Engineering +15

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators

Hiroyuki Mizuno, N. Matsuzaki, Kensuke Osada et al. · IEEE Journal of Solid-State Circuits · 1996 · 14 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 4.4-ns CMOS 54×54-b multiplier using pass-transistor multiplexer

N. Ohkubo, Makoto Suzuki, T. Shinbo et al. · 2002 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +16