D. Ingerly

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner et al. · 2012 · 749 citations

Low-power Cmos Technology, Engineering, Vlsi Design +19

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Peng Bai, C. Auth, S. Balakrishnan et al. · 2005 · 230 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15

Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices

D. Ingerly · 2019 · 149 citations

8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm², 1mm Package-on-Package

Wilfred Gomes, Sanjeev Khushu, D. Ingerly et al. · 2020 · 88 citations

Engineering, Computer Architecture, Embedded Systems +23

Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing

Wilfred Gomes, Altug Koker, Pat Stover et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 88 citations

Heterogeneous Computing, Engineering, Computer Architecture +19