Anindya Sundar Dhar - Concepedia

Author

Anindya Sundar Dhar

Indian Institute of Technology Kharagpur ORCID

Also Known As

A S Dhar, A. S. Dhar, A. Sundar Dhar, A.S. Dhar, Anindya S Dhar, Anindya S. Dhar, Anindya Sundar Dhar, Anindya.S. Dhar, Dhar, Anindya S., Dhar, Anindya Sundar

145

Publications

995

Citations

H-Index

Concepts

All Affiliations

Indian Institute of Technology Kharagpur Integrated Test Range

About

Anindya Sundar Dhar is an author at Indian Institute of Technology Kharagpur specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	15	28	649
2	Computer Engineering	15	28	649
3	Computer Science	11	14	327
4	Electrical Engineering	2	2	69
5	Biomedical Engineering	1	1	57

Anindya Sundar Dhar

Publications

675

Citations

H-Index

Page 1

	Year	Citations
CORDIC Architectures: A Survey B. Lakshmi, Anindya Sundar Dhar VLSI design Architectural DesignCordic AlgorithmEngineeringHardware AccelerationCordic Architectures	2010	81
FPGA realization of a CORDIC based FFT processor for biomedical signal processing Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee Microprocessors and Microsystems Medical ElectronicsEngineeringBiosignal ProcessingBioelectronicsFft Processor	2001	57
A VLSI array architecture for realization of DFT, DHT, DCT and DST Koushik Maharatna, Anindya Sundar Dhar, Swapna Banerjee Signal Processing Electrical EngineeringEngineeringVlsi DesignVlsi Array ArchitectureVlsi Architecture	2001	56
An array architecture for fast computation of discrete Hartley transform Anindya Sundar Dhar, Swapna Banerjee IEEE Transactions on Circuits and Systems Array ProcessingLinear ArraysArray ComputingEngineeringArray Architecture	1991	55
CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis Kailash Chandra Ray, Anindya Sundar Dhar IEE Proceedings - Circuits Devices and Systems Window FunctionsEngineeringVlsi DesignHardware AlgorithmComputer Architecture	2006	33
Real-time fault-tolerance with hot-standby topology for conditional sum adder Atin Mukherjee, Anindya Sundar Dhar Microelectronics Reliability Reliability EngineeringEngineeringComputer EngineeringComputer ArchitectureFault Tolerance	2015	32
Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar IEEE Transactions on Very Large Scale Integration (VLSI) Systems Adaptive FilterEngineeringVlsi Architecture DesignFiltering TechniqueProportionate-type Normalized Lms	2018	24
A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC Mrityunjoy Chakraborty, Anindya Sundar Dhar, Moon Ho Lee IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing Numerical AnalysisTrigonometric FormulationEngineeringLeast Mean SquareLms Algorithm	2005	23
Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar IEEE Transactions on Very Large Scale Integration (VLSI) Systems Logarithmic Number SystemNonlinear FilteringEngineeringHardware AlgorithmComputer Architecture	2017	23
VLSI architecture for low latency radix-4 CORDIC B. Lakshmi, Anindya Sundar Dhar Computers & Electrical Engineering EngineeringVlsi DesignVlsi ArchitectureAsic ImplementationComputer Engineering	2011	21

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