Kailash Chandra Ray - Concepedia

Author

Kailash Chandra Ray

Indian Institute of Technology Patna ORCID

Also Known As

K C Ray, K. C. Ray, K. Ray, K.C. Ray, Kailash Chandra Ray, Kailash C. Ray, Kailash Chandra Ray

Publications

1.4K

Citations

H-Index

Concepts

All Affiliations

Indian Institute of Technology Patna Indian Institute of Technology Kharagpur Indian Institute of Information Technology Allahabad

About

Kailash Chandra Ray is an author at Indian Institute of Technology Patna specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	15	20	923
2	Medicine	4	4	435
3	Public Health	2	2	49
4	Biomedical Engineering	1	1	44
5	Biostatistics	1	1	16

Kailash Chandra Ray

Publications

1.2K

Citations

H-Index

Page 1

	Year	Citations
ECG Signal Analysis Using DCT-Based DOST and PSO Optimized SVM Sandeep Raj, Kailash Chandra Ray IEEE Transactions on Instrumentation and Measurement Svm ClassifierElectrical EngineeringSupport Vector MachineEngineeringElectrophysiological Evaluation	2017	241
Sparse representation of ECG signals for automated recognition of cardiac arrhythmias Sandeep Raj, Kailash Chandra Ray Expert Systems with Applications Electrophysiological EvaluationEcg SignalsEngineeringSparse RepresentationPattern Recognition	2018	132
Cardiac arrhythmia beat classification using DOST and PSO tuned SVM Sandeep Raj, Kailash Chandra Ray, Om Shankar Computer Methods and Programs in Biomedicine Data ClassificationSupport Vector MachineElectrophysiological EvaluationBiosignal ProcessingSignal Processing	2016	108
Low Latency Hybrid CORDIC Algorithm Rohit Shukla, Kailash Chandra Ray IEEE Transactions on Computers Numerical AnalysisNumerical ComputationEngineeringHardware AccelerationHybrid Algorithm	2013	60
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder Amit Kumar Panda, Rakesh Palisetty, Kailash Chandra Ray IEEE Transactions on Circuits and Systems I Regular Papers EngineeringVlsi DesignHardware AccelerationVlsi ArchitectureHigh-performance Architecture	2020	55
Single cycle RISC-V micro architecture processor and its FPGA prototype Don Kurian Dennis, Ayushi Priyam, Sukhpreet Singh Virk, EngineeringComputer ArchitectureRisc-v ProcessorEmbedded SystemsProcessor Architecture	2017	48
Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation Amit Kumar Panda, Kailash Chandra Ray IEEE Transactions on Circuits and Systems I Regular Papers Hardware SecurityPseudorandom Bit GeneratorEngineeringVlsi DesignPseudorandom Bit Generation	2018	46
A Personalized Point-of-Care Platform for Real-Time ECG Monitoring Sandeep Raj, Kailash Chandra Ray IEEE Transactions on Consumer Electronics EngineeringRemote Patient MonitoringBiometricsWearable TechnologyFeature Extraction	2018	44
ARM-based arrhythmia beat monitoring system Sandeep Raj, G.S.S. Praveen Chand, Kailash Chandra Ray Microprocessors and Microsystems Electrophysiological EvaluationEngineeringBiosignal ProcessingWearable TechnologyPatient Monitoring	2015	43
A Coupled Variable Input LCG Method and its VLSI Architecture for Pseudorandom Bit Generation Amit Kumar Panda, Kailash Chandra Ray IEEE Transactions on Instrumentation and Measurement Hardware SecurityElectrical EngineeringEngineeringVlsi DesignPseudorandom Bit Generation	2019	43

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