Harijot Singh Bindra

Author

University of Twente ORCID

Also Known As

Harijot Singh Bindra

Publications

413

Citations

H-Index

Concepts

All Affiliations

University of Twente

About

Harijot Singh Bindra is an author at University of Twente specializing in computer engineering, engineering, and low-power electronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	6	6	364
2	Engineering	4	4	312
3	Education	1	1	50
4	Measurement	1	1	50
5	Microelectronics	1	1	50

Harijot Singh Bindra

Publications

392

Citations

H-Index

Page 1

	Year	Citations
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise Harijot Singh Bindra, Christiaan E. Lokin, Daniël Schinkel, IEEE Journal of Solid-State Circuits Low-power ElectronicsEngineeringDynamic Bias Pre-amplifierMixed-signal Integrated Circuit0.4-Mv Input Noise	2018	210
A 30fJ/comparison dynamic bias comparator Harijot Singh Bindra, Christiaan E. Lokin, Anne-Johan Annema, Energy ConsumptionEngineeringVlsi DesignLatch Type ComparatorMeasurement	2017	50
A 174μVRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch Harijot Singh Bindra, Jeroen Ponte, Bram Nauta 2022 IEEE International Solid- State Circuits Conference (ISSCC) Capacitive NeutralizationEngineeringClock RecoveryGs/s ComparatorData Converter	2022	41
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply Harijot Singh Bindra, Anne-Johan Annema, Gerard J. M. Wienk, Sar AdcDifferential Sar AdcNear Rail-to-rail InputData ConverterMixed-signal Integrated Circuit	2019	26
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator Harijot Singh Bindra, Anne-Johan Annema, Simon Louwsma, Flexible Sar AdcData ConverterMixed-signal Integrated CircuitAnalog DesignComputer Engineering	2019	26
Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging Joeri Lechevallier, Harijot Singh Bindra, Ronan van der Zee, IEEE Journal of Solid-State Circuits	2021	18
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC Harijot Singh Bindra, Anne-Johan Annema, Simon Louwsma, RadarLow-power ElectronicsSar AdcSampling (Signal Processing)Engineering	2017	11
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema,	2017	10

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