Harijot Singh Bindra

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

Harijot Singh Bindra, Christiaan E. Lokin, Daniël Schinkel et al. · IEEE Journal of Solid-State Circuits · 2018 · 210 citations · Full text

Low-power Electronics, Engineering, Dynamic Bias Pre-amplifier +10

A 30fJ/comparison dynamic bias comparator

Harijot Singh Bindra, Christiaan E. Lokin, Anne-Johan Annema et al. · 2017 · 50 citations

Energy Consumption, Engineering, Vlsi Design +13

A 174μVRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch

Harijot Singh Bindra, Jeroen Ponte, Bram Nauta · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 41 citations · Full text

Capacitive Neutralization, Engineering, Clock Recovery +11

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Harijot Singh Bindra, Anne-Johan Annema, Gerard J. M. Wienk et al. · 2019 · 26 citations · Full text

Sar Adc, Differential Sar Adc, Near Rail-to-rail Input +8

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator

Harijot Singh Bindra, Anne-Johan Annema, Simon Louwsma et al. · 2019 · 26 citations · Full text

Flexible Sar Adc, Data Converter, Mixed-signal Integrated Circuit +7