A 30fJ/comparison dynamic bias comparator

Abstract

A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with a modest reduction in input referred noise and 40% increase in CLK-Q delay for small differential input voltages.