A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS

Gregory K. Chen, Raghavan Kumar, H. Ekin Sumbul, +2

IEEE Journal of Solid-State Circuits

Flow ControlEngineeringNeural Networks (Machine Learning)Computer Architecture1M-synapse Chip +19

A Native Stochastic Computing Architecture Enabled by Memristors

Phil Knag, Wei Lü, Zhengya Zhang

IEEE Transactions on Nanotechnology

Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringComputational Neuroscience +13

DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware

Dewei Wang, Chuan-Tung Lin, Gregory K. Chen, +3

2022 IEEE International Solid- State Circuits Conference (ISSCC)

Convolutional Neural NetworkEngineeringComputer ArchitectureMulti-channel Memory ArchitectureHigh-performance Architecture +14

A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning

Jung Kuk Kim, Phil Knag, Thomas Chen, +1

EngineeringNeural Networks (Machine Learning)High ThroughputComputer ArchitectureNeurochip +19

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Phil Knag, Jung Kuk Kim, Thomas Chen, +1

IEEE Journal of Solid-State Circuits

Convolutional Neural NetworkEngineeringMachine LearningNeural Networks (Machine Learning)Autoencoders +23

Memristive devices for stochastic computing

Siddharth Gaba, Phil Knag, Zhengya Zhang, +1

Electrical EngineeringEngineeringSwitching TimeMemristive DevicesEmerging Memory Technology +10

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs

Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, +13

EngineeringMachine LearningAdvanced ComputingSmart Web SearchComputer Architecture +17

Characterization of Heavy-Ion-Induced Single-Event Effects in 65 nm Bulk CMOS ASIC Test Chips

Chia‐Hsiang Chen, Phil Knag, Zhengya Zhang

IEEE Transactions on Nuclear Science

Low-power ElectronicsElectrical EngineeringCross SectionEngineeringVlsi Design +12

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS

Phil Knag, Gregory K. Chen, H. Ekin Sumbul, +8

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignComputer ArchitectureBnn ChipIntegrated Circuits +17

A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS

Gregory K. Chen, Raghavan Kumar, H. Ekin Sumbul, +2

EngineeringMachine LearningNeural Network1M-synapse SnnSparse Weights +16