Anand Ramalingam

Sleep transistor sizing using timing criticality and temporal currents

Anand Ramalingam, Bin Zhang, Anirudh Devgan et al. · 2005 · 53 citations

Engineering, Vlsi Design, Power Optimization (Eda) +16

An accurate sparse matrix based framework for statistical static timing analysis

Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2006 · 39 citations

Engineering, Electronic Design Automation, Accurate Path-based Ssta +18

Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce

Anand Ramalingam, Anirudh Devgan, David Z. Pan · Journal of Low Power Electronics · 2007 · 19 citations

Power-aware Computing, Electrical Engineering, Engineering +15

Robust analytical gate delay modeling for low voltage circuits

Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan et al. · 2006 · 18 citations

Hardware Security, Low-power Electronics, Electrical Engineering +15

An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis

Anand Ramalingam, Gi-joon Nam, Ashish Singh et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2006 · 18 citations

Engineering, Electronic Design Automation, Accurate Path-based Ssta +18