D. Aneesh Bharadwaj

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Active since

2019

Affiliations

D. Aneesh Bharadwaj is an author at R.V. College of Engineering specializing in low-power design, phase-locked oscillators, and power consumption optimization.

Publications per year

2019–2021

Publications

Design and Implementation of High Frequency and Low-Power Phase-locked Loop

B. S. Premananda, T. N. Dhanush, Vaishnavi S. Parashar et al. · U Porto Journal of Engineering · 2021 · 17 citations · Full text

Engineering, Electrical Engineering, Low-power Design +16

Low Power AVLS-TSPC based 2/3 Pre-Scaler

P. Anirvinnan, Vaishnavi S. Parashar, D. Aneesh Bharadwaj · International Journal of Engineering and Advanced Technology · 2019 · 14 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +16

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