Clark Roberts

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

Sriram Vangal, Jason Howard, Greg Ruhl et al. · IEEE Journal of Solid-State Circuits · 2008 · 627 citations

Engineering, Computer Engineering, Computer Science +17

A 47$\,\times\,$10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS

Frank O’Mahony, James Jaussi, Joseph Kennedy et al. · IEEE Journal of Solid-State Circuits · 2010 · 62 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

Tawfiq Musah, James Jaussi, Ganesh Balamurugan et al. · IEEE Journal of Solid-State Circuits · 2014 · 59 citations

Engineering, Computer Engineering, Electrical Engineering +15

A Scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS

Mozhgan Mansuri, James Jaussi, Joseph Kennedy et al. · IEEE Journal of Solid-State Circuits · 2013 · 45 citations

Engineering, Computer Engineering, Electrical Engineering +17

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS

Mozhgan Mansuri, James Jaussi, Joseph Kennedy et al. · 2013 · 35 citations

Engineering, Computer Engineering, High-performance Computing +17