R. Schwencker

WiCkeD: analog circuit synthesis incorporating mismatch

K. Antreich, J. Eckmueller, Helmut Graeb et al. · 2002 · 73 citations

Engineering, Analog Cmos Circuits, Analog Integrated Circuits +12

Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search

F. Schenkel, Michael Pronath, S. Zizala et al. · 2001 · 63 citations

Physical Design (Electronics), Engineering, Circuit Design +14

The generalized boundary curve — a common method for automatic nominal design centering of analog circuits

R. Schwencker, F. Schenkel, Helmut Graeb et al. · 2000 · 28 citations

Numerical Analysis, Engineering, Electronic Design Automation +18

Analog circuit sizing using adaptive worst-case parameter sets

R. Schwencker, F. Schenkel, Michael Pronath et al. · Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition · 2003 · 25 citations

Physical Design (Electronics), Engineering, Circuit System +12

Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets

R. Schwencker, F. Schenkel, Michael Pronath et al. · Design, Automation, and Test in Europe · 2002 · 24 citations

Physical Design (Electronics), Engineering, Circuit System +12