Jan Plíva

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

Lukas Kull, Jan Plíva, Thomas Toifl et al. · IEEE Journal of Solid-State Circuits · 2016 · 75 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS

László Szilágyi, Jan Plíva, Ronny Henker et al. · IEEE Journal of Solid-State Circuits · 2018 · 45 citations

Engineering, Communication, Electrical Engineering +17

A 42-Gb/s VCSEL Driver Suitable for Burst Mode Operation in 14-nm Bulk CMOS

Mahdi Khafaji, Jan Plíva, Ronny Henker et al. · IEEE Photonics Technology Letters · 2017 · 19 citations

Engineering, Electrical Engineering, Microelectronics +15

A $4\times45$ Gb/s Two-Tap FFE VCSEL Driver in 14-nm FinFET CMOS Suitable for Burst Mode Operation

Mohammad Mahdi Khafaji, Guido Belfiore, Jan Plíva et al. · IEEE Journal of Solid-State Circuits · 2018 · 18 citations

Engineering, Electrical Engineering, Microelectronics +15

A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm<sup>2</sup> in 32 nm SOI CMOS

Lukas Kull, Jan Plíva, Thomas Toifl et al. · 2014 · 13 citations · Full text

Engineering, Electrical Engineering, Analog Electronics +12