Gunjan Pandya

Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs

Muhammad Khellah, Y. Ye, N. Kim et al. · 2006 · 85 citations

Electrical Engineering, Engineering, Vlsi Design +13

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process

Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya et al. · IEEE Journal of Solid-State Circuits · 2010 · 77 citations

Low-power Electronics, Electrical Engineering, Engineering +8

A 256-Kb Dual-${V}_{\rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor

Muhammad Khellah, Dinesh Somasekhar, Yibin Ye et al. · IEEE Journal of Solid-State Circuits · 2007 · 58 citations

Low-power Electronics, Sram Building Block, Electrical Engineering +13

Multi-phase 1GHz voltage doubler charge-pump in 32nm logic process

Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya et al. · 2009 · 34 citations

Low-power Electronics, Electrical Engineering, Engineering +8

A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS

Muhammad Khellah, Nam Sung Kim, Jason Howard et al. · 2006 · 31 citations

Low-power Electronics, Hardware Security, Electrical Engineering +11