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Process variability in sub-16nm bulk CMOS technology
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2012
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Electrical EngineeringPhysical Design (Electronics)Public NatureVlsi DesignEngineeringProcess VariabilityNanoelectronicsDeliverable D3.6Computer ArchitectureCmos TechnologyComputer EngineeringTechnologyMicroelectronicsTrams Project
The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.