A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.

Abstract

As modern areas of application for coarse-grained reconfigurable systems digital signal processing, multimedia in embedded devices, and wireless communication can be mentioned among others. These fields include different algorithms with varying complexity and speed requirements. In this paper a new highly parameterizable coarse-grained reconfigurable architecture called weakly programmable processor array is discussed. It consists of several weakly programmable processing elements with a VLIW (Very Large Instruction Word) architecture which are connected with the help of dynamically reconfigurable interconnect modules.