ScholarsArchive (Brigham Young University) · 2006 · 30 citations · 0 references
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EngineeringComputer EngineeringComputer ScienceComputer ArchitectureFault ToleranceFault-tolerant ComputingFpga ArchitectureHardware AccelerationHardware Fault ToleranceLow-power Fpga DesignTiming AnalysisFault-tolerant Fpga ArchitectureSingle Event Upset Modeling
Sponsorship: Department of Energy, Los Alamos National Laboratory. This document describes the methodology used to predict single-event upset rates for Xilinx Virtex FPGAs based on the CREME96 orbit modeling tool. Using this methodology, SEU upset rates are obtained for several Xilinx Virtex FPGAs including Virtex, Virtex-II, and Virtex-4. Further, SEU upset rates are obtained for a variety of orbits for each of these FPGAs.