A MULTILAYERED IMMUNE SYSTEM FOR HARDWARE FAULT TOLERANCE WITHIN AN EMBRYONIC ARRAY

Abstract

Biology demonstrates high levels of fault tolerance in all instances. This paper documents a demonstration system that takes inspiration from the immune system and embryonic processes to acquire some of these fault tolerant properties in hardware circuits. A multi-layer immune system is used as fault detection; a negative selection algorithm is used at a system level to identify non-self states. These are localised by further tests. Reconfiguration of the embryonic array accommodates the faults located. The detector set for the negative selection algorithm is currently derived by hand, although appropriate learning algorithms are identified and commented upon.