Sub-Nanometer Equivalent Oxide Thickness and Threshold Voltage Control Enabled by Silicon Seed Layer on Monolayer MoS₂ Transistors

Abstract

Low-power transistors based on two-dimensional (2D) semiconductors require ultrathin gate insulators, whose atomic layer deposition (ALD) has been difficult without adequate surface preparation. Here, we achieve sub-1 nm equivalent oxide thickness (EOT) on monolayer MoS 2 using HfO 2 and a simple, commonly available Si seed. We first investigate six seed layer candidates (Si, Ge, Hf, La, Gd, Al 2 O 3 ) and find that only Si and Ge cause no measurable damage to the MoS 2 . With these, we build monolayer MoS 2 transistors using ALD of HfO 2 top-gate dielectric and find that the Si seed provides the better, low-hysteresis interface. The thickness of this interfacial layer also controls the threshold voltage, enabling normally-off, well-behaved transistors. The thinnest gate stack reached low EOT ≈ 0.9 nm with low leakage (<0.6 μA/cm 2 ) and ∼80 mV/dec subthreshold swing at room temperature. This represents a simple top-gate dielectric deposition approach, achievable within many common nanofabrication facilities.