A fast and high-precision all-digital automatic calibration circuit that is highly suited for $\Delta \Sigma$ fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub- $f_{\rm REF}$ frequency resolution of $f_{\rm REF}/k$ in a time period of $k\cdot T_{\rm REF}$ . The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain $K_{\rm VCO}$ and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate $\Delta \Sigma$ modulator to achieve sub- $f_{\rm REF}$ calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9–3.8 GHz $\Delta \Sigma$ fractional-N synthesizer is implemented in 0.13 $\mu$ m CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1–6.0 $\mu$ s with ${\pm}2\hbox{\%}$ accuracy and the VCO frequency calibration is completed in 1.225–4.025 $\mu$ s, all across the entire octave tuning range.

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