BEOL-Compatible MFMIS Ferroelectric/Anti-Ferroelectric FETs—Part I: Experimental Results With Boosted Memory Window

Abstract

Through careful design of the area ratio (AR) of the back-end-of-line (BEOL)-compatible metal–ferroelectric–metal–insulator–semiconductor (MFMIS) ferroelectric field-effect transistor (FeFET), we are able to modulate the charge injection in the gate-stack and successfully extend the memory window (MW) to ~8 V, far beyond the theoretical limit of double coercive voltage (Vc) for the Fe layer within the gate-stack. Moreover, we have developed and demonstrated, for the first time, the BEOL-compatible antiferroelectric (AFe) FET with the same MFMIS structure by substituting the Fe HfxZr1-xO2 (HZO) to Zr-rich AFe HZO. By adjusting the AR and channel thickness, either volatile or nonvolatile memory can be realized with the same structure. Meanwhile, the MW of anti-FeFETs (AFeFETs) up to ~3 V further confirms the influence of the charging effect. Furthermore, we have validated the reliability of both Fe and AFeFETs, demonstrating decent endurance and retention time. As the operation voltage for AFeFETs can be smaller than their Fe counterparts, they hold great promise to achieve ultrahigh-endurance operation. We have even confirmed an endurance over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{9}}$ </tex-math></inline-formula> cycles without apparent MW degradation and dielectric breakdown for the AFeFETs when operating with unipolar voltage.