IEEE Transactions on Circuits & Systems II Express Briefs · 2023 · 14 citations · 20 references
EngineeringComputer EngineeringComputer ScienceComputer VisionField-programmable Gate ArraysReconfigurable ComputingAccelerator ArchitectureField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationLow-power Fpga DesignRadar SystemsActivity RecognitionConvolutional Neural NetworksEnergy-efficient Hardware AccelerationField-programmable Gate Arrays (Fpgas)Human Activity RecognitionPower-efficient Accelerator DesignRadar Hardware ArchitectureReconfigurable Hardware Architecture
Radar-based human activity recognition (HAR) has great potential in many applications. The deployment of HAR in many practical applications requires the system to be energy-resource efficient. In this work, we propose a lightweight dedicated hardware accelerator for radar-based HAR. In particular, the specific property of radar signals are taken advantages of to optimize the 1-D convolutional neural network (CNN) model for HAR. Based on that, a dedicated hardware architecture is further proposed to exploit the advantages of the optimized CNN model. We build a prototype system on field programmable gate array (FPGA) to validate and demonstrate the proposed design. We also map the proposed accelerator to 55nm CMOS technology. Experimental results show that the performance as well as the energy-resource efficiency of the proposed design are significantly higher than other existing vision-based HAR systems.
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Deep learning for sensor-based activity recognition: A survey
Jindong Wang, Yiqiang Chen, Shuji Hao et al. · Pattern Recognition Letters · 2018 · 1.9K citations · Full text
Improving Neural Networks with Dropout
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