A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques

Abstract

This paper presents a power-efficient constant-slope digital-to-time converter (DTC) with embedded nonlinearity cancellation. By utilizing the capacitor based digital-to-analog converter (C-DAC) to adjust the initial voltage of the discharging process, the DTC achieves a fine resolution of < 600-fs. Sources of nonlinearity are quantitatively analyzed, followed by circuit implementations that intrinsically cancel them. The range-extension technique is proposed to increase the range of the DTC by a factor of two without further complicating the capacitor array. The power consumption of the DTC is reduced by the self-power down technique that automatically detects the end of the conversion and shuts off the current. The proposed DTC consumes 120- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> at 50-MHz clock rate. It achieves a fine resolution of 563-fs over a 10-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.14/0.96-LSB, respectively.