Ultrathin Gate Dielectric Enabled by Nanofog Aluminum Oxide on Monolayer MoS₂

Abstract

Field-effect transistors (FETs) based on two-dimensional (2D) semiconductors must have ultrathin gate dielectrics in order to achieve low voltage operation. Here we achieve conformal HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> gate dielectrics on monolayer MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> with the aid of an AlO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> seed layer deposited by "nanofog," a low temperature process at 50 °C. We study the uniformity of the nanofog layer as a function of its deposition temperature, and we also compare FETs fabricated with nanofog AlO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> seed vs. electron-beam evaporated Al seed layers, followed by HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> dielectric. With the nanofog seed, we achieve subthreshold slope < 100 mV/dec at room temperature and equivalent oxide thickness (EOT) of 1.3 nm. Devices with nanofog exhibit nearly hysteresis-free behavior, unlike those with the Al seed, consistent with the subthreshold data showing fewer interface defects with nanofog seed layers. The "nanofog" process is thus established as a low-temperature, industry-compatible seed layer for high-κ dielectric deposition onto 2D semiconductors.