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Highly Stable Short Channel Ultrathin Atomic Layer Deposited Indium Zinc Oxide Thin Film Transistors With Excellent Electrical Characteristics
17
Citations
28
References
2023
Year
Materials ScienceSemiconductorsElectrical EngineeringExcellent Electrical CharacteristicsEngineeringElectronic MaterialsSemiconductor TechnologyOxide ElectronicsApplied PhysicsSemiconductor NanostructuresHigh-performance Atomic LayerSemiconductor MaterialThin FilmsAmorphous InznoSemiconductor DeviceGate Stability
The high-performance atomic layer deposited (ALD) ultrathin (~2 nm) amorphous InZnO ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${a}$ </tex-math></inline-formula> -IZO, indium: Zinc ≈ 6:4) channel thin-film transistors (TFTs) with a short channel length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{L}_{\mathbf {\textit {ch}}}$ </tex-math></inline-formula> ) of 50 nm were presented. Furthermore, the gate stability was evaluated using temperature-dependent positive-bias stress (PBS) tests for the IZO TFTs up to 3.5 MV/cm. The short channel TFTs exhibited excellent electrical characteristics, with high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\mathbf {\textit {on}}}$ </tex-math></inline-formula> exceeding <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$360~\mu \text{A} / \mu \text{m}$ </tex-math></inline-formula> (@ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathbf {G}}$ </tex-math></inline-formula> = 2V), and an optimized threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathbf {\textit {th}}}$ </tex-math></inline-formula> ) of ~ 0.11 V. In particular, the ultra-low drain-induced barrier lowering (DIBL) performance of 16 mV/V was presented and matched with technology computer aided design (TCAD) estimation. The activation energy of device degradation was extracted to better understand the mechanism. The extracted high field effect channel mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\mathbf {\textit {FE}}}$ </tex-math></inline-formula> ) of 43.6 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\mathbf {{2}}}$ </tex-math></inline-formula> /V-s in conjunction with the low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathbf {\textit {th}}}$ </tex-math></inline-formula> shifts of 12.4 mV (@ 3.5 MV/cm; <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathbf {\textit {th}}}$ </tex-math></inline-formula> +2V) for 5000s PBS test at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25^{\mathbf {o}}$ </tex-math></inline-formula> C exhibited the excellent performances combining channel mobility and gate stability reported for oxide semiconductor TFT.
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