Near-Ideal Top-Gate Controllability of InGaZnO Thin-Film Transistors by Suppressing Interface Defects with an Ultrathin Atomic Layer Deposited Gate Insulator

Abstract

An ultrathin atomic-layer-deposited (ALD) AlO_<i>x</i> gate insulator (GI) was implemented for self-aligned top-gate (SATG) amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Although the 4.0-nm thick AlO_<i>x</i> exhibited ideal insulating properties, the interaction between ALD AlO_<i>x</i> and predeposited a-IGZO caused a relatively defective interface, thus giving rise to hysteresis and bias stress instabilities. As analyzed using high-resolution transmission electron microscopy, X-ray photoelectron spectroscopy, and the Hall measurement, the chemical reaction between the ALD precursor and a-IGZO is revealed. This was effectively prevented by preoxidizing a-IGZO with nitrous oxide (N₂O) plasma. With 4 nm-AlO_<i>x</i> GI and low-defect interfaces, high performance and stability were simultaneously achieved on SATG a-IGZO TFTs, including a near-ideal record-low subthreshold swing of 60.8 mV/dec, a low operation voltage below 0.4 V, a moderate mobility of 13.3 cm²/V·s, a low off-current below 10^-13 A, a large on/off ratio over 10⁹, and negligible threshold-voltage shifts less than 0.04 V against various bias-temperature stresses. This work clarifies the vital interfacial reaction between top-gate high-<i>k</i> dielectrics and amorphous oxide semiconductors (AOSs) and further provides a feasible way to remove this obstacle to downscaling SATG AOS TFTs.