Top-Gate CVD WSe₂ pFETs with Record-High I_d~594 μA/μm, G_m~244 μS/μm and WSe₂/MoS₂ CFET based Half-adder Circuit Using Monolithic 3D Integration

Abstract

Monolithic integration of complementary field-effect transistor (CFET) with two-dimensional (2D) materials channels has been challenging due to the deteriorated performance of p-type transistors, especially using top-gate dielectric. In this work, we demonstrate monolithic 3D stacking CFET based on chemical-vapor-deposition (CVD) grown 2D materials channels for low-power integrated circuits (ICs). The top gate p-channel bilayer WSe <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> transistor is optimized by low-temperature post-metal annealing, achieving a record-high $\text{I}_{\text{o}\text{n}}$ of -594$\mu$A/$\mu$m and $\text{G}_{\text{m}}$ of -244$\mu$S/$\mu$m at $\text{V}_{\text{d}}=-2$V with a short $\text{L}_{\text{c}\text{h}}=135$ nm, far exceeding previous results. Furthermore, full-output-swing inverters with rail-to-rail operations and below-nanowatt low power are achieved owing to the symmetrical threshold voltages for WSe <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> pFETs and MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> nFETs. The 4T SRAM and 16T half-adder circuit units based on CFET design are also experimentally demonstrated for the first time, presenting the superiority of CFET in performance, power, and area (PPA).