A Hybrid Computing-In-Memory Architecture by Monolithic 3D Integration of BEOL CNT/IGZO-based CFET Logic and Analog RRAM

Abstract

Here we present a hybrid computing-in-memory (CIM) architecture, named M3D-CCP, by monolithically 3D integration of Si CMOS logic layer, RRAM-based CIM layer and processing-near-memory (PNM) layer with CNT/IGZO-based complementary field-effect transistor (CFET). The Si-CMOS layer was fabricated using a standard 130 nm process and served as control logic. The CIM layer consisted of ITIR arrays with analog resistive random-access memory (RRAM) for matrix-vector multiplication (MVM) operations in neural networks. The CFET-based PNM layer was fabricated with carbon nanotube FET (CNT-FET) and InGaZn$\text{O}_{\text{x}}$ FET (IGZO-FET) for caching and processing data between layers of neural networks. Both the CIM and PNM layers were fabricated using a low-temperature ($\leq$300 °c) backend-of-the-line (BEOL) process. The structural integrity and proper function of each layer were verified. Furthermore, an image super-resolution task was implemented using the fabricated M3D-CCP chip, achieving GPU-equivalent performance on the DVI2K dataset with $149\times$ lower energy consumption. Our work demonstrates the feasibility and great potential of such hybrid CIM architecture for data-abundant applications such as artificial intelligence (AI) and high-performance computing (HPC).