CMOS Demonstration of Negative Capacitance HfO₂-ZrO₂ Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process

Abstract

We report on the successful integration of a low equivalent oxide thickness (EOT) negative capacitance (NC) gate stack – a 1.8 nm ferroelectric-antiferroelectric (FE-AFE) HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -ZrO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> superlattice (HZH) [1] – into a 90 nm CMOS R&D technology, following a self-aligned, replacement gate process. The integrated gate oxides show an effective oxide thickness (EOT) of 7.5 Å on both p - and n-SOI MOSFETs. This amounts to a 2Å EOT lowering compared to conventional high-$\kappa$ dielectric HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> due to the NC effect. Large intrinsic transconductance at $90\text{nm}L_{g},1.0\text{mS}/\mu\text{m}$ and $1.5\text{mS}/\mu\text{m}$ for p-FETs and n-FETs, respectively, exceeding L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> scaling trends for industry benchmarks, are demonstrated. The low EOT also increases the $90\text{nm}L_{g}\text{ON}$-current to levels approaching reports of semiconductor foundry nodes at much lower $L_{g}(\sim 30\text{nm})$. Successful CMOS circuits are also demonstrated.