Publication | Open Access
A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator
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2022
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This paper presents the first continuous-time (CT) noise-shaping SAR (NS-SAR) ADC. Different from the prior discrete-time (DT) NS-SAR ADCs in literature, this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT-operated SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty-cycled. Fabricated in 65 nm CMOS, the prototype achieves 77 dB peak SNDR within 62.5 kHz bandwidth while consuming 13.5 μW, and it provides 15 dB anti-aliasing in the alias band.