Memory Window Expansion for Ferroelectric FET based Multilevel NVM: Hybrid Solution with Combination of Polarization and Injected Charges

Abstract

The memory window (MW) of a metal-ferroelectric-semiconductor (MFS)-based ferroelectric field-effect transistor (FE-FET) is generally 2V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> , where V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> is the coercive voltage of the FE layer. When applying the program and erase voltages, adverse charge injection from the gate metal or the channel likely occurs. While the latter decreases the MW, the former may further increase it over 2V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> , which is highly useful for the multilevel FE-FET. In this work, we propose a metal-insulator-ferroelectric-semiconductor (MIFS)-based FE-FET to widen the MW by providing additional charges at the gate metal/ferroelectric interface. When part of the injected charges are retained at the polarization switching, the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> increases, and thus, MW also increases. This is due to the additional voltage drop by the injected charge exchange at the moment of FE switching. For a given FE layer thickness, the MW of MIFS-stacked FE-FET was expanded by ∼55% compared to MFS-stacked FE-FET.