2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) · 2022 · 27 citations · 17 references
ComputingComputer EngineeringComputer ScienceFault ToleranceFault-tolerant ComputingMachine LearningDeep LearningDevice ReliabilityError CorrectionFault DetectionHardware Fault ToleranceNeural NetworksAccuracyBit Error RateBit-error Rate AnalysisFault-tolerant Machine LearningFault-tolerant NetworksParity BitsStorage Overhead OptimizationTraining Processes
Deep neural networks (DNNs) are deployed on hardware devices and are widely used in various fields to perform inference from inputs. Unfortunately, hardware devices can become unreliable by incidents such as unintended process, voltage and temperature variations, and this can introduce the occurrence of erroneous weights. Prior study reports that the erroneous weights can cause a significant accuracy degradation. In safety-critical applications such as autonomous driving, it can bring catastrophic results. Retraining or fine-tuning can be used to adjust corrupted weights to prevent the accuracy degradation. However, training-based approaches would incur a significant computational overhead due to a massive size of training datasets and intensive training operations. Thus, this paper proposes a value-aware parity insertion error correction code (ECC) to recover erroneous weights with a reduced parity storage overhead and no additional training processes. Previous ECC-based reliability improvement methods, Weight Nulling and In-place Zero-space ECC, are compared with the proposed method. Experimental results demonstrate that DNNs with the value-aware parity insertion ECC can perform inference without the accuracy degradation, on average, in 122.5× and 15.1× higher bit error rate conditions over Weight Nulling and In-place Zero-space ECC, respectively.
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